39 lines
946 B
Verilog
39 lines
946 B
Verilog
`timescale 1 ps/1 ps
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// extracted from altera_mf.v
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module bug2011429;
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reg pass = 1'b1;
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reg [7:0] vco_tap;
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reg vco_c0_last_value;
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integer c_ph_val[0:5];
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always @(vco_tap[c_ph_val[0]])
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vco_c0_last_value = vco_tap[c_ph_val[0]];
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initial begin
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vco_tap = 8'b10101010;
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c_ph_val[0] = 0;
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#1;
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if (vco_c0_last_value != 1'b0) begin
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$display("FAILED initial value, got %b", vco_c0_last_value);
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pass = 1'b0;
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end
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vco_tap = vco_tap >> 1;
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#1;
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if (vco_c0_last_value != 1'b1) begin
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$display("FAILED shifted value, got %b", vco_c0_last_value);
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pass = 1'b0;
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end
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c_ph_val[0] = 1;
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#1;
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if (vco_c0_last_value != 1'b0) begin
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$display("FAILED index change, got %b", vco_c0_last_value);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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