60 lines
1.1 KiB
Verilog
60 lines
1.1 KiB
Verilog
`define PERIOD 10
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module main;
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reg CLK;
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integer counter;
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initial begin // reset and clock generator
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counter = 0;
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CLK = 0;
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#2; // wait 2, and then...
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repeat(10) // generate 5 clock cycles
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#(`PERIOD/2) CLK = !CLK;
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$display("time %0t; the counter is %0d", $time, counter);
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$finish(0);
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end
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task test1;
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begin
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@(posedge CLK);
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$display("test1 increment; reading counter as %0d", counter);
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// the function call is necessary to get the problem
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counter = _$Fadd32(counter, 1'b1);
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end
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endtask
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task test2;
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begin
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@(posedge CLK);
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$display("test2 increment; reading counter as %0d", counter);
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counter = _$Fadd32(counter, 1'b1);
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end
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endtask
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function [31:0] _$Fadd32;
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input l,r;
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reg [31:0] l,r;
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_$Fadd32 = l+r;
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endfunction
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endmodule // main
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module trig1;
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always begin
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#`PERIOD;
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top.main.test1;
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end
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endmodule
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module trig2;
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always begin
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#`PERIOD;
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top.main.test2;
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end
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endmodule
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module top;
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main main();
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trig1 trig1();
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trig2 trig2();
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endmodule
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