40 lines
711 B
Verilog
40 lines
711 B
Verilog
module top;
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reg pass = 1'b1;
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reg a, b;
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real c, d;
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initial begin
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c = 0.0;
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d = 1.0;
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a = 1'b0;
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b = 1'b0;
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assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
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#1;
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if (c != 3.0) begin
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$display("FAILED, expected 3.0, got %f", c);
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pass = 1'b0;
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end
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a = 1'b1;
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b = 1'b0;
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assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
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#1;
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if (c != 2.0) begin
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$display("FAILED, expected 2.0, got %f", c);
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pass = 1'b0;
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end
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a = 1'b0;
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b = 1'b1;
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assign c = 6/(2 - d*(b & ~a) + d*(a & ~b));
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#1;
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if (c != 6.0) begin
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$display("FAILED, expected 6.0, got %f", c);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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