29 lines
715 B
Verilog
29 lines
715 B
Verilog
module tern;
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reg [13:0] fdbk_err_wide;
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// arithmetic saturation from 14 bits down to 13 bits, and drop lsb
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wire [11:0] fdbk_err = ((fdbk_err_wide[13:12]==2'b00) | (fdbk_err_wide[13:12]==2'b11)) ?
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fdbk_err_wide[12:1] : {fdbk_err_wide[13],{11{~fdbk_err_wide[13]}}};
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initial begin
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#10;
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$display(fdbk_err_wide, fdbk_err);
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// 2008-03-04 snapshot prints x x, 2008-04-02 git prints x z
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// 01eb298228d0adce9d62818e21d47fb274af9060 is first "bad" commit
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#10;
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fdbk_err_wide = 42;
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#10;
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$display(fdbk_err_wide, fdbk_err);
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// everybody agrees this is 42 21
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#10;
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fdbk_err_wide = 14'bxxxxxxxxxxxxxx;
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#10;
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// everybody agrees this is x x
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$display(fdbk_err_wide, fdbk_err);
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#10;
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$finish(0);
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end
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endmodule
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