12 lines
346 B
Verilog
12 lines
346 B
Verilog
module top;
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parameter one = 1'b1;
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parameter zero = 1'b0;
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// These should fail since a zero replication is invalid in this context.
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wire [3:0] ca_tru = one ? 4'b0001 : {0{1'b0}};
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wire [3:0] ca_fal = zero ? {0{1'b0}} : 4'b0010;
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// We used to not check for this so just pass for that case
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initial $display("PASSED");
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endmodule
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