18 lines
309 B
Verilog
18 lines
309 B
Verilog
module top;
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reg [1:0] in;
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subm sm [1:0](in);
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initial begin
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// This should trigger instance 0.
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in[0] = 0;
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#1 in[0] = 1;
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// This should trigger instance 1.
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in[1] = 0;
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#1 in[1] = 1;
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end
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endmodule
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module subm(input wire in);
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always @(posedge in) $display("In %m at %0t", $time);
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endmodule
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