37 lines
619 B
Verilog
37 lines
619 B
Verilog
module top;
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reg pass = 1'b1;
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reg [1:0] in;
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wire out;
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function IS_NOT_ZERO;
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input [3:0] in;
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begin
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IS_NOT_ZERO = |in;
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end
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endfunction
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assign out = (IS_NOT_ZERO(in) == 1'b1);
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initial begin
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in = 2'b00;
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#1 if (out != 1'b0) begin
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$display("Failed for 2'b00 case.");
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pass = 1'b0;
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end
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in = 2'b01;
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#1 if (out != 1'b1) begin
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$display("Failed for 2'b01 case.");
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pass = 1'b0;
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end
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in = 2'b10;
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#1 if (out != 1'b1) begin
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$display("Failed for 2'b01 case.");
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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