34 lines
670 B
Verilog
34 lines
670 B
Verilog
`timescale 1us/100ns
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module top;
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reg pass = 1'b1;
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real ra = 1.0;
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wire real rufunc;
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assign #10 rufunc = rl_func(ra);
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initial begin
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#1 if (rufunc == 2.0) begin
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pass = 1'b0;
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$display("Real: user function value (%f) not delayed.", rufunc);
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end
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#8 if (rufunc == 2.0) begin
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pass = 1'b0;
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$display("Real: user function value (%f) not delayed.", rufunc);
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end
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#2;
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if (rufunc != 2.0) begin
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pass = 1'b0;
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$display("Real: user function value not delayed correctly.");
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end
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if (pass) $display("PASSED");
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end
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function real rl_func;
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input real in;
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rl_func = in * 2.0;
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endfunction
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endmodule
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