19 lines
459 B
Verilog
19 lines
459 B
Verilog
module top;
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wire real result;
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reg [63:0] bits;
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// This generates incorrect code:
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// The .net/real temporary is not needed.
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// The .alias/real temporary is not needed.
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// The .sfunc should connect directly to the "results" net.
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// The .part is not needed and is causing a core dump.
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assign result = $bitstoreal(bits);
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initial begin
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$monitor("%g %h", result, bits);
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bits = 64'b0;
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#1 bits = {1'b0,{62{1'b1}}};
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end
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endmodule
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