26 lines
327 B
Verilog
26 lines
327 B
Verilog
module top;
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wire real vo;
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rcvr U1(vo);
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drvr U2(vo);
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endmodule
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module rcvr(vo);
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input vo;
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wire real vo;
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always @(vo)
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$display("Real value is %f at %g", vo, $time);
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endmodule
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module drvr(vo);
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output vo;
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reg real vo;
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initial begin
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vo = 3.3;
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#1000 vo = 4.5776;
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#1000 vo = -4;
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end
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endmodule
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