23 lines
348 B
Verilog
23 lines
348 B
Verilog
// pr1855504
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module mul_test();
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reg [15:0] prod;
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reg [7:0] op2;
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reg [15:0] op1;
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initial begin
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op1 = 16'h0DA0;
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op2 = 8'h0A;
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prod = 16'h0000;
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end
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always begin
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prod <= op1[7:0] * op2;
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#5 $display("op1 = %h, op2 = %h, prod = %h", op1, op2, prod);
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#5 $finish(0);
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end
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endmodule // mul_test
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