25 lines
447 B
Verilog
25 lines
447 B
Verilog
// Copyright 2007, Martin Whitaker.
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// This file may be freely copied for any purpose.
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module memory_monitor();
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reg [7:0] Memory[0:15];
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reg [3:0] Index;
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wire Flag1;
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wire FlagI;
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assign Flag1 = (Memory[1] == 0);
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assign FlagI = (Memory[Index] == 0);
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initial begin
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Index = 1;
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Memory[Index] = 0;
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#1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
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Memory[Index] = 1;
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#1 $display("Flag1 = %b, FlagI = %b", Flag1, FlagI);
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end
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endmodule
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