44 lines
906 B
Verilog
44 lines
906 B
Verilog
module shift;
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reg pass = 1'b1;
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integer i;
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reg [7:0] foo;
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parameter [2:0]
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ZERO = 0,
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THREE = 3;
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initial begin
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foo = 1'b1 << ZERO;
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if (foo != 'd1) begin
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$display("FAILED shift by ZERO, got %d expected 1", foo);
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pass = 1'b0;
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end
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foo = 1'b1 << THREE;
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if (foo != 'd8) begin
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$display("FAILED shift by THREE, got %d expected 8", foo);
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pass = 1'b0;
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end
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foo = 1'b1 << 3;
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if (foo != 'd8) begin
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$display("FAILED shift by 3, got %d expected 8", foo);
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pass = 1'b0;
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end
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foo = 1'b1 << 'd3;
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if (foo != 'd8) begin
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$display("FAILED shift by 'd3, got %d expected 8", foo);
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pass = 1'b0;
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end
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i = 'd3;
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foo = 1'b1 << i;
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if (foo != 'd8) begin
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$display("FAILED shift by variable set to 'd3, got %d expected 8", foo);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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