32 lines
438 B
Verilog
32 lines
438 B
Verilog
`begin_keywords "1364-2005"
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module main;
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wire y1, y2, y3;
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reg a;
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initial begin
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$monitor($time , " y1 = %d, y2 = %d, y3 = %d, a = %d", y1, y2, y3, a);
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#1 a = 1;
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#1 a = 0;
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end
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sub s1(y1, y2, y3, a);
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endmodule // main
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module sub(y1, y2, y3, a);
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output y1, y2, y3;
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input a;
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reg y1, y2, y3;
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reg int;
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always @(*) begin
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y1 <= a;
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y2 <= y1;
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int <= a;
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y3 <= int;
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end
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endmodule
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`end_keywords
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