50 lines
760 B
Verilog
50 lines
760 B
Verilog
`begin_keywords "1364-2001-noconfig"
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// Copyright 2007, Martin Whitaker.
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// This code may be freely copied for any purpose.
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module gen_param_test();
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localparam W = 3;
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localparam D = 3;
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reg [W-1:0] A[1:D];
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reg [W-1:0] B[1:D];
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wire [W-1:0] Y[1:D];
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generate
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genvar j;
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for (j = 1; j <= D; j = j + 1) begin:sum
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adder #(W) instance(A[j], B[j], Y[j]);
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end
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endgenerate
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integer i;
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initial begin
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for (i = 1; i <= D; i = i + 1) begin
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A[i] = i - 1;
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B[i] = i + 1;
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end
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#1;
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for (i = 1; i <= D; i = i + 1) begin
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$display("%d + %d = %d", A[i-1], B[i-1], Y[i-1]);
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end
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end
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endmodule
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module adder #(parameter W = 1) (
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input wire [W-1:0] A,
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input wire [W-1:0] B,
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output wire [W-1:0] Y
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);
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assign Y = A + B;
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endmodule
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`end_keywords
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