38 lines
777 B
Verilog
38 lines
777 B
Verilog
`begin_keywords "1364-2005"
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// pr1745005
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//
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module main;
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reg [31:0] ref;
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reg [3:0] addr;
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wire [3:0] out_net1 = ref[{addr,2'b00} +: 4];
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wire [3:0] out_net2 = ref[{addr,2'b11} -: 4];
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reg [3:0] out_reg;
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initial begin
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ref = 32'h76543210;
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for (addr = 0 ; addr < 8 ; addr = addr+1) begin
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#1 ;
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out_reg = ref[{addr,2'b00} +: 4];
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if (out_reg !== addr) begin
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$display("FAILED -- addr=%d, out_reg=%b", addr, out_reg);
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$finish;
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end
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if (out_net1 !== addr) begin
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$display("FAILED -- addr=%d, out_net1=%b", addr, out_net1);
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$finish;
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end
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if (out_net2 !== addr) begin
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$display("FAILED -- addr=%d, out_net2=%b", addr, out_net2);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule
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`end_keywords
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