311 lines
8.5 KiB
Verilog
311 lines
8.5 KiB
Verilog
/**
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* Author: Evan Lavelle, Riverside Machines Ltd.
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* Version: 0.1 (2007-05-22)
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* Licence: This code is released into the public domain.
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*
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* Test implicit Verilog-95 style ports. According to 12.3.2 of the 2005
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* LRM:
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*
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* "The port reference for each port in the list of ports at the top of each
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* module declaration can be one of the following:
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*
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* A simple identifier or escaped identifier
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* A bit-select of a vector declared within the module
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* A part-select of a vector declared within the module
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* A concatenation of any of the above
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*
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* The port expression is optional because ports can be defined that do not
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* connect to anything internal to the module."
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*
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* The expected output is:
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*
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* sum[ 1] = 0101010101100000
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* sum[ 2] = 0101010101100000
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* sum[ 3] = 0101010101100000
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* sum[ 4] = 0101010101100000
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* sum[ 5] = 0101010101100000
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* sum[ 6] = 0101010101100000
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* sum[ 7] = 0101010101100000
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* sum[ 8] = 0101010101100000
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* sum[ 9] = 0101010101100000
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* sum[ 10] = 0101010101100000
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* sum[ 11] = 0101010101100000
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* sum[ 12] = 0101010101100000
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* sum[ 13] = 0101010101100000
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* sum[ 14] = 0101010101100000
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* sum[ 15] = 0101010101100000
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* sum[ 16] = 0101010101100000
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* sum[ 17] = 0101010101100000
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* sum[ 18] = 0101010101100000
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* sum[ 19] = 0101010101100000
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* sum[ 20] = 0101010101100000
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* sum[ 21] = 0101010101100000
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* sum[ 22] = 0101010101100000
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* sum[ 23] = 0101010101100000
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*
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*/
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module test;
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reg [15:0] sum[23:1];
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wire [7:0] data = 1;
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wire dummy1, dummy2;
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wire [15:0] wire5, wire9, wire13, wire17, wire21;
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initial
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main;
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task main;
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integer i;
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begin
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for(i=1; i<=23; i=i+1)
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sum[i] = 'h555f;
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#2;
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sum[5] = wire5;
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sum[9] = wire9;
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sum[13] = wire13;
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sum[17] = wire17;
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sum[21] = wire21;
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for(i=1; i<=23; i=i+1)
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$display("sum[%d] = %b", i, sum[i]);
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end
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endtask
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m1 m1();
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m2 m2(dummy1, dummy2);
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m3 m3(dummy1, , dummy2);
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m4 m4(data);
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m5 m5(data, wire5);
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m6 m6(dummy1, data);
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m7 m7(data, );
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m8 m8 (data);
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m9 m9 (data, wire9);
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m10 m10( , data);
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m11 m11(data, );
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m12 m12(data[0]);
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m13 m13(data[0], wire13);
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m14 m14( , data[0]);
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m15 m15(data[0], );
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m16 m16(data);
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m17 m17(data, wire17);
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m18 m18(dummy1, data);
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m19 m19(data, );
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m20 m20(data);
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m21 m21(data, wire21);
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m22 m22(dummy1, data);
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m23 m23(data, );
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endmodule
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/* ----------------------------------------------------------------------------
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* the test modules
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* ------------------------------------------------------------------------- */
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// 95, no ports
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module m1;
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initial #1 test.sum[1] = test.sum[1] + test.data;
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endmodule
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// 95, two ports, but neither has an internal connection
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module m2(,);
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initial #1 test.sum[2] = test.sum[2] + test.data;
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endmodule
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// 95, three ports, but none have an internal connection
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module m3(,,);
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initial #1 test.sum[3] = test.sum[3] + test.data;
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endmodule
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/* ----------------------------------------------------------------------------
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* 95, one and two ports, with implicit and simple identifiers
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* ------------------------------------------------------------------------- */
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// 95, one implicit port, simple identifier
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module m4(a);
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input a;
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wire [7:0] a;
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initial #1 test.sum[4] = test.sum[4] + a;
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endmodule
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// 95, two implicit ports, simple identifiers
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module m5(a, b);
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input a;
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output b;
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wire [7:0] a;
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reg [15:0] b;
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initial #1 b <= test.sum[5] + a;
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endmodule
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// 95, two ports; the first has no internal connection; the second is implicit/
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// simple
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module m6(,a);
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input a;
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wire [7:0] a;
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initial #1 test.sum[6] = test.sum[6] + a;
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endmodule
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// 95, two ports; the second has no internal connection; the first is implicit/
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// simple
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module m7(a,);
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input a;
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wire [7:0] a;
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initial #1 test.sum[7] = test.sum[7] + a;
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endmodule
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/* ----------------------------------------------------------------------------
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* 95, one and two ports, with implicit and extended identifiers
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* ------------------------------------------------------------------------- */
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// 95, one implicit port, extended identifier
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module m8(\a );
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input \a ;
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wire [7:0] \a ;
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initial #1 test.sum[8] = test.sum[8] + \a ;
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endmodule
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// 95, two implicit ports, extended identifiers
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module m9(\a , \b );
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input \a ;
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output \b ;
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wire [7:0] \a ;
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reg [15:0] \b ;
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initial #1 \b = test.sum[9] + \a ;
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endmodule
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// 95, two ports; the first has no internal connection; the second is implicit/
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// extended
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module m10(,\a );
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input \a ;
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wire [7:0] \a ;
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initial #1 test.sum[10] = test.sum[10] + \a ;
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endmodule
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// 95, two ports; the second has no internal connection; the first is implicit/
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// extended
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module m11(\a ,);
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input \a ;
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wire [7:0] \a ;
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initial #1 test.sum[11] = test.sum[11] + \a ;
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endmodule
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/* ----------------------------------------------------------------------------
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* 95, one and two ports, with implicit and vector bit-select ports
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* ------------------------------------------------------------------------- */
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// 95, one implicit port, vector bit-select
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module m12(a[0]);
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input a;
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wire [7:0] a;
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initial #1 test.sum[12] = test.sum[12] + {test.data[7:1], a[0]};
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endmodule
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// 95, two implicit ports, vector bit-selects. the output is actually a part
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// select, since ISE core dumps on the assign below, and doing anything
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// else in -95 is difficult
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module m13(a[0], b[15:0]);
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input a;
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output b;
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wire [7:0] a;
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reg [31:0] b;
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reg [15:0] temp;
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// assign test.wire13[15:1] = temp[15:1]; // drives the rest of wire13
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initial begin
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#1 temp = test.sum[13] + {test.data[7:1], a[0]};
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b = temp; // drives wire13[0]
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end
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endmodule
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// 95, two ports; the first has no internal connection; the second is implicit/
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// vector bit-select
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module m14(,a[0]);
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input [7:0] a;
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initial #1 test.sum[14] = test.sum[14] + {test.data[7:1], a[0]};
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endmodule
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// 95, two ports; the second has no internal connection; the first is implicit/
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// vector bit-select
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module m15(a[0],);
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input [7:0] a;
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initial #1 test.sum[15] = test.sum[15] + {test.data[7:1], a[0]};
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endmodule
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/* ----------------------------------------------------------------------------
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* 95, one and two ports, with implicit and vector part-select ports
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* ------------------------------------------------------------------------- */
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// 95, one implicit port, vector bit-select
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module m16(a[7:0]);
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input a;
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wire [15:0] a;
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initial #1 test.sum[16] = test.sum[16] + {8'h00, a[7:0]};
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endmodule
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// 95, two implicit ports, vector bit-selects
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module m17(a[7:0], b[15:0]);
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input a;
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output b;
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wire [7:0] a;
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reg [31:0] b;
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initial #1 b[15:0] = test.sum[17] + a;
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endmodule
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// 95, two ports; the first has no internal connection; the second is implicit/
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// vector part-select
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module m18(,a[7:0]);
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input [15:0] a;
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initial #1 test.sum[18] = test.sum[18] + {8'h00, a[7:0]};
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endmodule
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// 95, two ports; the second has no internal connection; the first is implicit/
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// vector part-select
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module m19(a[7:0],);
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input [15:0] a;
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// initial #1 test.sum[19] = test.sum[19] + a;
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initial #1 test.sum[19] = test.sum[19] + {8'h00, a[7:0]};
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endmodule
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/* ----------------------------------------------------------------------------
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* 95, one and two ports, with ports which are a concatenation of a bit select
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* and a 3-bit part select
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* ------------------------------------------------------------------------- */
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// 95, one implicit port, concatenation
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module m20({a[7], a[6:0]});
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input a;
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wire [15:0] a;
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initial #1 test.sum[20] = test.sum[20] + {8'h00, a[7:0]};
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endmodule
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// 95, two implicit ports, concatenations
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module m21({a[7], a[6:0]}, {b[15], b[14:0]});
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input a;
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output b;
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wire [7:0] a;
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reg [15:0] b;
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initial #1 b = test.sum[21] + {8'h00, a[7:0]};
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endmodule
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// 95, two ports; the first has no internal connection; the second is implicit/
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// concatenation
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module m22(,{a[7], a[6:0]});
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input [15:0] a;
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initial #1 test.sum[22] = test.sum[22] + {8'h00, a[7:0]};
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endmodule
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// 95, two ports; the second has no internal connection; the first is implicit/
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// concatenation. note that both modelsim and ISE set the entire sum, and not
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// just the top 8 bits, to all x's for 'test.sum[23] = test.sum[23] + a'
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module m23({a[7], a[6:0]},);
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input a;
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wire [15:0] a;
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initial #1 test.sum[23] = test.sum[23] + a[7:0];
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endmodule
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