69 lines
1.8 KiB
Verilog
69 lines
1.8 KiB
Verilog
/*
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This incorrect code causes iverilog 20070421 and earlier to dump core.
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$ iverilog -t null empty_param.v
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Segmentation Fault - core dumped
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*/
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module param_test (clk, reset_n, test_expr);
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parameter severity_level = 1;
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parameter width = 32;
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parameter property_type = 0;
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input clk, reset_n;
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input [width-1:0] test_expr;
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endmodule
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module empty_param;
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reg clk;
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reg [3:0] fsm;
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// An empty parameter like is easy to cause with an undefined macro
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// expanding to null
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param_test #( , 4) submod(clk, 1'b1, fsm);
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initial begin
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if (submod.severity_level !== 1) begin
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$display("FAILED -- severity_level = %d", submod.severity_level);
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$finish;
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end
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if (submod.width !== 4) begin
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$display("FAILED -- width = %d", submod.width);
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$finish;
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end
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if (submod.property_type !== 0) begin
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$display("FAILED -- property_type = %d", submod.property_type);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule
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/* Copyright (C) 1999 Stephen G. Tell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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* n
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this software; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
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* Boston, MA 02111-1307 USA
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*
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*/
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