28 lines
569 B
Verilog
28 lines
569 B
Verilog
module main;
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wire [1:0] foo [0:1];
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assign (highz0, strong1) foo[0] = 2'b01;
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assign (strong0, highz1) foo[0] = 2'b01;
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assign (highz0, strong1) foo[1] = 2'b10;
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assign (strong0, highz1) foo[1] = 2'b10;
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initial begin
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#1 $display("foo[0] = %b, foo[1] = %b", foo[0], foo[1]);
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if (foo[0] !== 2'b01) begin
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$display("FAILED -- foo[0] = %b", foo[0]);
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$finish;
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end
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if (foo[1] !== 2'b10) begin
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$display("FAILED == foo[1] = %b", foo[1]);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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