26 lines
427 B
Verilog
26 lines
427 B
Verilog
// pr1697250
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module test();
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wire active;
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reg [63:0] bus;
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assign active = ((|(bus)===0)?0:1);
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initial begin
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bus = 'haaaa;
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#1 if (active !== 1) begin
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$display("FAILED -- bus=%h, active=%b", bus, active);
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$finish;
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end
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bus = 0;
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#1 if (active !== 0) begin
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$display("FAILED == bus=%h, active=%b", bus, active);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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