31 lines
432 B
Verilog
31 lines
432 B
Verilog
module test ();
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reg[7:0] a;
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reg b;
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always @*
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begin
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b = 1'b0;
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case (a)
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8'd66: b = 1'b1;
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default: ;
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endcase
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end
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initial begin
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a = 0;
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#1 if (b !== 0) begin
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$display("FAILED -- a=%h b=%b", a, b);
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$finish;
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end
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a = 66;
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#1 if (b !== 1) begin
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$display("FAILED -- a=%h b=%b", a, b);
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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