22 lines
487 B
Verilog
22 lines
487 B
Verilog
`define EOF -1
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module bar;
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integer line, rc, file, a, b, c;
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reg [8*256:1] str;
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initial begin
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file = $fopen ("ivltests/pr1687193.dat", "r");
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if (file == 0)
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$finish;
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for (line = 1; line <= 5; line = line + 1) begin
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rc = $fgets (str, file);
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if (rc == `EOF)
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$finish;
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rc = $sscanf (str, "%h %h %h\n", a, b, c);
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$display ("\tLine %d matches %d args: %h %h %h", line, rc, a, b, c);
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end
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$fclose (file);
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$finish(0);
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end
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endmodule
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