53 lines
787 B
Verilog
53 lines
787 B
Verilog
// pr1662508.v
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`timescale 1ns / 1ns
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module ram(
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input clk,
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input we,
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input [9:0] addr,
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input [15:0] data,
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output [15:0] read_bus
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);
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reg [15:0] ram[31:0];
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assign read_bus = ram[addr[3:0]];
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always @(posedge clk) if (we)
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ram[addr[3:0]] <= data;
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endmodule
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module ram_test;
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reg clk;
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reg fail=0;
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integer cc;
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initial begin
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for (cc = 0; cc < 33; cc=cc+1) begin
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clk = 0; #5;
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clk = 1; #5;
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end
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if (fail) $display("FAIL");
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else $display("PASSED");
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end
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reg we=0;
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reg [9:0] addr=0;
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reg [15:0] data=0;
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always @(posedge clk) begin
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addr <= cc;
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data <= cc*cc;
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we <= cc<16;
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end
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wire [15:0] read_bus;
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ram ram(clk, we, addr, data, read_bus);
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always @(negedge clk) if (~we) begin
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$display("%d %d", addr, read_bus);
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if (read_bus !== addr[3:0]*addr[3:0]) fail=1;
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end
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endmodule
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