28 lines
419 B
Verilog
28 lines
419 B
Verilog
module RegisterArrayBug01;
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reg [15:0] rf[0:7];
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wire [15:0] rf_0 = rf[1];
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initial begin
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$monitor($time,, "rf[0] is %h %h", rf[1], rf_0);
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rf[1] = 16'hffff;
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#10 rf[1] = 16'h0000;
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#10 rf[1] = 16'hbeef;
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#10 $finish(0);
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end
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endmodule
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/*
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System prints:
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0 rf[0] is xxxx ffff
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10 rf[0] is xxxx 0000
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20 rf[0] is beef beef
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Expected is:
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0 rf[0] is ffff ffff
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10 rf[0] is 0000 0000
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20 rf[0] is beef beef
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*/
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