36 lines
616 B
Verilog
36 lines
616 B
Verilog
`timescale 1ns/1ns
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module top;
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reg [7:0] data;
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reg [9:0] odata;
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reg sout, clk;
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integer lp;
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initial begin
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data = 8'h55;
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#0 $display("Printing the byte %b with a header.", data);
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$write("Bad - ");
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odata = 10'b1x00000000;
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odata[7:0] = data;
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send_byte(odata);
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// #0 send_byte(odata); // This fixes things, but should not be needed!
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$write(", ok - ");
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send_byte(odata);
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$display(".");
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#1 data = 0;
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#1 $finish(0);
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end
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// Print a byte of data.
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task send_byte;
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input [9:0] sndbyte;
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begin
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$write("%b", sndbyte);
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end
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endtask
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endmodule
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