24 lines
425 B
Verilog
24 lines
425 B
Verilog
/* PR1625912 */
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/*
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* Substatuting in either of the commented out lines caused VVP to fail.
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*/
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module top;
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integer cnt;
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real result, win;
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initial begin
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cnt = -10;
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for (result=-10; result<=10; result=result+2) begin
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#1 if (result != cnt) begin
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$display("FAILED -- cnt=%0d, result=%f", cnt, result);
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end
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cnt = cnt + 2;
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end
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$display("PASSED");
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$finish;
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end
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endmodule
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