25 lines
446 B
Verilog
25 lines
446 B
Verilog
module test ();
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wire [2:0] d [0:2];
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reg [2:0] src[0:2];
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genvar i;
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for (i = 0 ; i < 3 ; i = i+1)
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assign d[i] = src[i];
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integer idx;
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initial begin
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for (idx = 0 ; idx < 3 ; idx = idx+1)
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src[idx] = idx;
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#1 for (idx = 0 ; idx < 3 ; idx = idx+1)
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if (d[idx] !== idx) begin
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$display("FAILED -- d[%0d] = %b", idx, d[idx]);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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