25 lines
508 B
Verilog
25 lines
508 B
Verilog
module main;
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reg signed [5:0] GAIN = 2;
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reg signed [23:0] iir = -8;
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wire signed [23:0] iir_s1 = iir >>> 2;
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wire signed [23:0] iir_s2 = iir >>> GAIN;
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initial begin
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#1 /* Wait for inputs values to settle. */ ;
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if (iir_s1 !== -24'sd2) begin
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$display("FAILED -- s1 = %d (%h)", iir_s1, iir_s1);
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$finish;
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end
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if (iir_s2 !== -24'sd2) begin
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$display("FAILED -- s2 = %d (%h)", iir_s2, iir_s2);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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