35 lines
731 B
Verilog
35 lines
731 B
Verilog
module math(a, b, c, z);
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input signed [19:0] a, b;
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input signed [24:0] c;
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output signed [24:0] z;
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assign z = a + b + c - (c >>> 1);
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endmodule
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module test();
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reg signed [19:0] a, b;
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reg signed [24:0] z, c;
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wire signed [24:0] y;
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wire signed [24:0] w = a + b + c - (c >>> 1);
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math m(a,b,c,y);
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initial begin
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a = -5;
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$display("a = %x %d", a, a);
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b = 0;
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$display("b = %x %d", b, b);
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c = 8;
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$display("c = %x %d", c, c);
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z = a + b + c - (c >>> 1);
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#1 /* delay for things to settle. */;
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$display("z = %x, %d, %b", z, z, z);
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$display("y = %x, %d, %b", y, y, y);
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$display("w = %x, %d, %b", w, w, w);
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$display("%b %b %b %b", $is_signed(a),
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$is_signed(b), $is_signed(c), $is_signed(c >>> 1));
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end
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endmodule
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