44 lines
1.4 KiB
Verilog
44 lines
1.4 KiB
Verilog
//
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// Copyright (c) 2000 Steve Wilson (stevew@home.com)
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//
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// This source code is free software; you can redistribute it
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// and/or modify it in source code form under the terms of the GNU
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// General Public License as published by the Free Software
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// Foundation; either version 2 of the License, or (at your option)
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// any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program; if not, write to the Free Software
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// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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//
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// for3.16A - Template 1 - for(val1=0; val1 <= expr ; val1 = val1 + 1) some_action
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//
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module pr1120 ();
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wire [31:0] foo;
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reg [31:0] bar;
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// FAIL
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assign foo[31:16] = (bar & 32'hffffffff) >> 16;
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// PASS
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//assign foo[31:16] = bar >> 16;
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initial
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begin
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bar = 32'ha5a5_3f3f;
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#100;
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$display("foo[31:16] = %x bar = %x",foo[31:16],bar);
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//if(foo[31:16]==((bar & 32'hffffffff) >> 16))
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if(foo[31:16] === 16'ha5a5)
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$display("PASS (%x)",foo[31:16]);
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else
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$display("FAIL (%x vs %x)",foo[31:16],((bar & 32'hffffffff) >> 16));
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$finish;
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end
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endmodule
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