25 lines
419 B
Verilog
25 lines
419 B
Verilog
/*
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* This test reflects the problem reported in PR#1115.
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*/
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module test;
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reg[7:0] addr [0:2], pixel;
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wire match0 = addr[0] == pixel;
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initial begin
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pixel = 1;
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addr[0] = 1;
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addr[1] = 2;
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addr[2] = 3;
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#1 if (match0 !== 1'b1) begin
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$display("FAILED -- match0 is %b", match0);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule
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