33 lines
576 B
Verilog
33 lines
576 B
Verilog
/*
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* This test program catches the essence of PR#1072
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*/
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module main;
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parameter WIDTH = 4;
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wire [19:0] foo = { 1<<WIDTH {1'b1}};
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reg [19:0] bar;
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initial begin
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#1 bar = { 1<<WIDTH {1'b1}};
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if (foo !== 20'h0ffff) begin
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$display("FAILED -- foo = %b", foo);
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$finish;
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end
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if (bar !== 20'h0ffff) begin
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$display("FAILED -- bar = %b", bar);
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$finish;
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end
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if (foo !== bar) begin
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$display("FAILED -- foo !== bar (%h !== %h)", foo, bar);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule
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