54 lines
1.0 KiB
Verilog
54 lines
1.0 KiB
Verilog
module test;
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reg d;
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wire bar;
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// Assign some value to bar with weak drive.
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assign (weak0, weak1) bar = d;
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// Whatever value is on bar, give that *strong* drive onto foo.
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// The strength of an assignment is its own, and does not come
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// from the strength contained in the r-value.
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tri0 foo = bar;
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initial begin
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d = 0;
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#1 if (d !== bar) begin
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$display("FAILED -- d=%b, bar=%b", d, bar);
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$finish;
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end
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if (d !== foo) begin
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$display("FAILED -- d=%b, foo=%b", d, foo);
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$finish;
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end
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d = 1;
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#1 if (d !== bar) begin
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$display("FAILED -- d=%b, bar=%b", d, bar);
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$finish;
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end
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if (d !== foo) begin
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$display("FAILED -- d=%b, foo=%b", d, foo);
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$finish;
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end
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d = 'bz;
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#1 if (d !== bar) begin
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$display("FAILED -- d=%b, bar=%b", d, bar);
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$finish;
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end
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if ('b0 !== foo) begin
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$display("FAILED -- d=%b, foo=%b", d, foo);
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$finish;
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end
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$display("PASSED");
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$finish;
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end // initial begin
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endmodule // test
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