39 lines
1006 B
Verilog
39 lines
1006 B
Verilog
module top;
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reg passed = 1'b1;
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reg [199:0] r, a, b;
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initial begin
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a = 'd5;
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b = 'd2; // A simple test.
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r = a ** b;
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if (r != 'd25) begin
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$display("Failed: 5 ** 2 gave %d, expected 25", r);
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passed = 1'b0;
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end
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b = 'd55; // A 128 bit value.
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r = a ** b;
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if (r != 200'd277555756156289135105907917022705078125) begin
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$display("Failed: 5 ** 55\n gave %0d", r);
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$display(" expected 277555756156289135105907917022705078125");
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passed = 1'b0;
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end
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b = 'd86; // A 200 bit value.
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r = a ** b;
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if (r != 200'd1292469707114105741986576081359316958696581423282623291015625) begin
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$display("Failed: 5 ** 55\n gave %0d", r);
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$display(" expected 1292469707114105741986576081359316958696581423282623291015625");
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passed = 1'b0;
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end
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if (r != 'd5**'d86) begin
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$display("Failed: compile-time/run-time value mismatch.");
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passed = 1'b0;
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end
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if (passed) $display("PASSED");
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end
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endmodule
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