46 lines
922 B
Verilog
46 lines
922 B
Verilog
module top;
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reg pass;
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integer in1, in2, res;
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initial begin
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pass = 1'b1;
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in1 = 1; in2 = 2;
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res = in1 ** in2;
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if (res != 1) begin
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$display("Failed: 1 ** 2, expected 1, got %0d", res);
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pass = 1'b0;
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end
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in1 = 2; in2 = 3;
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res = in1 ** in2;
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if (res != 8) begin
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$display("Failed: 2 ** 3, expected 8, got %0d", res);
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pass = 1'b0;
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end
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in1 = -2; in2 = 2;
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res = in1 ** in2;
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if (res != 4) begin
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$display("Failed: -2 ** 2, expected 4, got %0d", res);
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pass = 1'b0;
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end
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in1 = -2; in2 = 3;
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res = in1 ** in2;
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if (res != -8) begin
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$display("Failed: -2 ** 3, expected -8, got %0d", res);
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pass = 1'b0;
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end
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in1 = 1; in2 = -1;
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res = in1 ** in2;
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if (res != 1) begin
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$display("Failed: 1 ** -1, expected 1, got %0d", res);
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pass = 1'b0;
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end
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if (pass) $display("PASSED");
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end
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endmodule
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