21 lines
378 B
Verilog
21 lines
378 B
Verilog
/***********************************************************************
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Duplicate input declaration test case
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Duplicate port declarations should generate an error
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***********************************************************************/
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module port_test4 (
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a, // Input
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b, // Output
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);
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input a;
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input a;
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output b;
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assign b=a;
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endmodule
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