29 lines
478 B
Verilog
29 lines
478 B
Verilog
// This is a regression test for the bug fixed in patch tracker #1268.
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module test();
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reg [19:0] a[15:0];
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reg [3:0] idx[3:1];
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initial begin
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idx[1] = 2;
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idx[2] = 3;
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idx[3] = 4;
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a[idx[1]][idx[2]*4 +: 4] <= #(idx[3]) 4'ha;
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#4;
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$display("%h", a[2]);
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if (a[2] !== 20'hxxxxx) begin
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$display("FAILED");
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$finish;
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end
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#1;
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$display("%h", a[2]);
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if (a[2] !== 20'hxaxxx) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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