63 lines
1.3 KiB
Verilog
63 lines
1.3 KiB
Verilog
module main;
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reg enable, bar_a, bar_b, val_in;
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reg [7:0] scon;
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reg val;
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//(* ivl_synthesis_on *)
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always @(val_in or bar_a or bar_b or scon[7:6] or enable)
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begin
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if (scon[7:6]==2'b10) begin
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val = 1'b1;
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end else if (enable) begin
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val = val_in;
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end else begin
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val = !bar_b & bar_a;
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end
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end
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(* ivl_synthesis_off *)
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initial begin
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val_in = 0;
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enable = 0;
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bar_b = 0;
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bar_a = 0;
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scon = 8'b10_000000;
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#1 if (val !== 1'b1) begin
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$display("FAILED -- scon=%b, val=%b", scon, val);
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$finish;
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end
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scon = 0;
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enable = 1;
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#1 if (val !== 1'b0) begin
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$display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
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$finish;
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end
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val_in = 1;
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#1 if (val !== 1'b1) begin
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$display("FAILED -- scon=%b, enable=%b, val_in=%b, val=%b",
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scon, enable, val_in, val);
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$finish;
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end
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enable = 0;
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#1 if (val !== 1'b0) begin
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$display("FAILED -- scon=%b, enable=%b, val=%b", scon, enable, val);
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$finish;
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end
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bar_a = 1;
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#1 if (val !== 1'b1) begin
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$display("FAILED -- scon=%b, enable=%b, bar_a==%b, bar_b=%b, val=%b",
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scon, enable, bar_a, bar_b, val);
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$finish;
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end
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$display("PASSED");
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end
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endmodule // main
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