32 lines
660 B
Verilog
32 lines
660 B
Verilog
// This tests SystemVerilog packages
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//
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// This tests the elaboration infrastructure of packages in
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// SystemVerilog. It actually covers a fair number of features,
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// given the small size of the program:
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//
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// *) Parsing of package blocks and import statements
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// *) Manage scope of names in package
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// *) Actual references of imported names from packages.
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//
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package pkg;
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parameter int foo = 1;
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endpackage
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module test ();
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// import all from p1
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import pkg::*;
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initial begin
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$display("pkg::foo = %0d", foo);
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if (foo != 1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule // test
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