21 lines
367 B
Verilog
21 lines
367 B
Verilog
// Check that parameter declared in the module body can not be overridden by a
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// defparam if the module has a parameter port list.
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module a #(parameter A = 1);
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// This behaves like a localparam
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parameter B = 2;
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initial begin
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$display("FAILED");
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end
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endmodule
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module test;
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a i_a();
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defparam i_a.A = 10;
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defparam i_a.B = 20; // Error
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endmodule
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