23 lines
340 B
Verilog
23 lines
340 B
Verilog
// Check that parameter declared in the module body can not be overridden if the
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// module has a parameter port list.
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module a #(
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parameter A = 1
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);
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// This behaves like a localparam
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parameter B = 1;
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initial begin
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$display("FAILED");
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end
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endmodule
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module test;
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a #(
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.A(10),
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.B(20) // Error
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) i_a();
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endmodule
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