18 lines
458 B
Verilog
18 lines
458 B
Verilog
// Tests that it possible to omit the `parameter` keyword in a parameter port
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// list before changing the parameter type in SystemVerilog. In Verilog this is
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// not allowed and should result in an error.
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module a #(parameter real A = 1.0, integer B = 2);
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initial begin
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if (A == 10.1 && B == 20) begin
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$display("PASSED");
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end else begin
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$display("FAILED");
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end
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end
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endmodule
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module test;
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a #(.A(10.1), .B(20)) i_a();
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endmodule
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