71 lines
2.1 KiB
Verilog
71 lines
2.1 KiB
Verilog
/*
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* Copyright (c) 2001 Brendan J Simon
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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//****************************************************************************
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//
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// MODULE : parameter_test
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//
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// DESCRIPTION : Test module to demonstrate parameter evaluation bug.
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//
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// AUTHOR : Brendan J Simon (brendan.simon@bigpond.com)
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//
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// DATE : Monday 5th January 2001.
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//
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// NOTES : It seems that Icarus Verilog 0.4 does not evaluate
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// moderately complex parameter statements properly.
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//
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//****************************************************************************
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module parameter_test;
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parameter foo_size = 32 * 6;
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parameter foo_lsb = 0;
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`ifdef GOOD_CODE
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parameter foo_msb_temp = foo_lsb + foo_size;
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parameter foo_msb = foo_msb_temp - 1;
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`else
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parameter foo_msb = foo_lsb + foo_size - 1;
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`endif
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// These complex statements work;
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parameter temp0 = 1 + 2 + 3 + 4 + 5;
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parameter temp1 = 1 + 2 + 3 + 4 + 5 - 1;
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reg [foo_msb:foo_lsb] foo;
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integer i;
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initial begin
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for (i=0; i<foo_size; i=i+1) begin
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foo[i] = 1;
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end
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$write("foo = %0h\n", foo);
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$finish(0);
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end
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endmodule
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//****************************************************************************
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// EOF : parameter_test
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//****************************************************************************
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