55 lines
1.6 KiB
Verilog
55 lines
1.6 KiB
Verilog
/*
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* Copyright (c) 2001 Peter Bain
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*
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* This source code is free software; you can redistribute it
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* and/or modify it in source code form under the terms of the GNU
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* General Public License as published by the Free Software
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* Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
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*/
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/* This is based on PR#124. */
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`timescale 1ns/1ns
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module paramtest(clk, dat);
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parameter dat_width = 32;
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input clk;
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output [dat_width-1:0] dat;
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reg [dat_width-1:0] dat;
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reg [4-1:0] exp_dat;
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parameter pay_init = 32'h01020304;
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parameter pay_inc = 32'h01010101;
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parameter cell_size = (53 * 8);
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parameter transfers = cell_size/dat_width + ((cell_size%dat_width)?1:0);
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initial begin
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exp_dat = 0;
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dat = 0;
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end
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initial begin
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#10;
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for (exp_dat = 0; exp_dat != 4'hf; exp_dat = exp_dat + 1) begin
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dat <= exp_dat;
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#1
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if (dat !== exp_dat) begin
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$display("ERROR: dat = %h, exp_dat = %h", dat, exp_dat);
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end else begin
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$display("OKAY: dat = %h, exp_dat = %h", dat, exp_dat);
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end
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end
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end
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endmodule
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