33 lines
586 B
Verilog
33 lines
586 B
Verilog
/*
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* This example is a distillation of the essence of PR#993.
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* Or at least the essence that led to a bug report.
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*/
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module main;
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parameter [31:0] fifo_address = 32'hc0_00_00_00;
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reg [31:0] bar;
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reg flag;
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wire [31:0] foo = flag? fifo_address : bar;
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initial begin
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bar = ~fifo_address;
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flag = 1;
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#1 if (foo !== fifo_address) begin
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$display("FAILED");
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$finish;
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end
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flag = 0;
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#1 if (foo !== bar) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // main
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