55 lines
1.1 KiB
Verilog
55 lines
1.1 KiB
Verilog
/*
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* This program demonstrates non-constant part selects
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* applied to a parameter value.
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*/
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module main;
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parameter foo = 32'h76543210;
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reg [3:0] tmp;
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reg [3:0] idx;
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initial begin
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if (foo[0 +: 4] !== 4'h0) begin
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$display("FAILED -- %b !== 0", foo[0 +: 4]);
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$finish;
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end
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if (foo[4 +: 4] !== 4'h1) begin
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$display("FAILED -- %b !== 1", foo[4 +: 4]);
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$finish;
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end
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if (foo[8 +: 4] !== 4'h2) begin
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$display("FAILED -- %b !== 2", foo[8 +: 4]);
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$finish;
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end
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if (foo[12+: 4] !== 4'h3) begin
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$display("FAILED -- %b !== 3", foo[12 +: 4]);
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$finish;
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end
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for (idx = 0 ; idx < 8 ; idx = idx + 1) begin
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tmp = foo[(idx*4) +: 4];
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if (tmp !== idx) begin
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$display("FAILED -- %b !== %b", idx, tmp);
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$finish;
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end
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end
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for (idx = 0 ; idx < 8 ; idx = idx + 1) begin
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tmp = foo[(idx*4+3) -: 4];
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if (tmp !== idx) begin
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$display("FAILED -- %b !== %b", idx, tmp);
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$finish;
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end
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end
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$display("PASSED");
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end
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endmodule // main
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