31 lines
433 B
Verilog
31 lines
433 B
Verilog
// Invalid packed dimensions
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// This should generate a error message and not crash during elaboration
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typedef logic [] T1;
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typedef logic [0] T2;
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typedef logic [-1] T3;
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typedef logic [$] T4;
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module test (
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input [] port_a,
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input [0] port_b,
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output [-1] port_c,
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output [$] port_d
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);
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logic [$] a;
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T1 b;
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T1 [$] c;
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logic [0] d;
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T2 e;
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T2 [0] f;
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logic [-1] g;
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T3 h;
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T3 [-1] i;
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logic [$] j;
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T4 k;
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T4 [$] l;
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endmodule
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