61 lines
1.2 KiB
Verilog
61 lines
1.2 KiB
Verilog
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module test(input wire load, in,
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output reg out1, out2);
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(* ivl_combinational *)
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always @* begin
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out1 = 0;
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if (load) begin
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out1 = in;
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out2 = in;
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end else begin
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out2 = ~in;
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end
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end
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endmodule // test
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module test_bench;
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reg load;
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reg val;
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wire out1, out2;
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test DUT(.load(load), .in(val), .out1(out1), .out2(out2));
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(* ivl_synthesis_off *)
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initial begin
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val = 0;
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load = 1;
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#1 ;
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if (out1 !== 0 || out2 !== 0) begin
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$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
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$finish;
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end
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val = 1;
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#1 ;
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if (out1 !== 1 || out2 !== 1) begin
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$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
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$finish;
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end
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load = 0;
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#1 ;
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if (out1 !== 0 || out2 !== 0) begin
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$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
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$finish;
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end
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val = 0;
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#1 ;
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if (out1 !== 0 || out2 !== 1) begin
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$display("FAILED -- load=%b, val=%b, out1=%b, out2=%b", load, val, out1, out2);
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$finish;
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end
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$display("PASSED");
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end // initial begin
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endmodule // test_bench
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