25 lines
323 B
Verilog
25 lines
323 B
Verilog
module test();
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reg a, b, c;
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always @* begin // always @(b or c)
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a = b;
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$display("Triggered 1 at %0t", $time);
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@* a = c; // @(c)
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$display("Triggered 2 at %0t", $time);
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end
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initial begin
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#10 a = 0;
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#10 a = 1;
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#10 b = 0;
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#10 b = 1;
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#10 c = 0;
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#10 c = 1;
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#10 c = 0;
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#10 $finish(0);
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end
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endmodule
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