29 lines
677 B
Verilog
29 lines
677 B
Verilog
module main;
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reg [2:0] a;
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wire e0 = a==3'h0; wire n0 = a!=3'h0;
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wire e1 = a==3'h1; wire n1 = a!=3'h1;
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wire e2 = a==3'h2; wire n2 = a!=3'h2;
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wire e3 = a==3'h3; wire n3 = a!=3'h3;
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wire e4 = a==3'h4; wire n4 = a!=3'h4;
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wire e5 = a==3'h5; wire n5 = a!=3'h5;
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wire e6 = a==3'h6; wire n6 = a!=3'h6;
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wire e7 = a==3'h7; wire n7 = a!=3'h7;
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initial begin
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for (a=0; a<7; a=a+1) begin
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#1;
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$display("a=",a);
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$display(" 0 %d %d", e0, n0);
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$display(" 1 %d %d", e1, n1);
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$display(" 2 %d %d", e2, n2);
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$display(" 3 %d %d", e3, n3);
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$display(" 4 %d %d", e4, n4);
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$display(" 5 %d %d", e5, n5);
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$display(" 6 %d %d", e6, n6);
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$display(" 7 %d %d", e7, n7);
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end
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end
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endmodule
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